Key facts
- Brand
- ZiLOG
- Model
- Z80
- Category
- Other Electronics
- Documents
- 7
- Languages
- EN
- Last added
- 2012-06-12
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ZiLOG Z80 CPU Peripherals User Manual
This manual provides a complete description of the Z80 CPU peripheral family, covering counter/timer channels, direct memory access, serial I/O, parallel I/O, and related control logic. It includes architecture overviews, register descriptions, programming modes, and timing diagrams for each peripheral block.
Detailed sections explain interrupt daisy‑chain operation, RETI handling, and nested interrupt servicing, as well as pin assignments for various PLCC packages. The document serves engineers and developers who need to integrate or program Z80 peripheral chips in their designs.
ZiLOG Z80 specifications
| Operating clock frequency | 50 MHz |
|---|---|
| Ethernet interface | 10/100 Base‑T Ethernet PHY with RJ45 connector |
| SRAM | 512 KB fast SRAM |
| On‑chip Flash memory | 256 KB |
| Off‑chip NOR Flash memory | 1 MB |
| General‑purpose I/O pins | 32 5 V‑tolerant pins |
| Supply voltage | 3.0 V to 3.6 V (3.3 V nominal) |
| Operating temperature range | 0 °C to +70 °C |
| Package | 144‑pin LQFP |
| Board dimensions | 63.5 mm × 78.7 mm |
Source: ZILOG eZ80F917050SBCG Zdots SBC for eZ80AcclaimPlus Connectivity ASSP Product Specification
All ZiLOG Z80 documents by type
Day-to-day operation, settings and troubleshooting. Start here if the product is already set up.
Ratings, dimensions and ordering codes, for selection and design work.
Questions answered in these manuals
What is the clock speed of the eZ80F91 core used in the Zdots SBC?
The eZ80F91 core runs at a factory‑default frequency of 50 MHz.
From: ZILOG eZ80F917050SBCG Zdots SBC for eZ80AcclaimPlus Connectivity ASSP Product Specification
What type of Ethernet interface does the Zdots SBC provide?
It provides a 10/100 Base‑T Ethernet PHY with an RJ45 connector.
From: ZILOG eZ80F917050SBCG Zdots SBC for eZ80AcclaimPlus Connectivity ASSP Product Specification
What does the OUTD instruction do?
OUTD transfers a byte from the memory location pointed to by HL to an I/O port selected by register C, then decrements B and HL.
How many T‑states does the OTDR instruction take at 4 MHz?
At 4 MHz, OTDR requires 5.25 T‑states per execution when B ≠ 0, and 4 T‑states when B = 0.