dsPIC33F Family Data Sheet, contains product features and application information
The dsPIC33F family consists of high‑performance 16‑bit digital signal controllers designed for general‑purpose and motor‑control applications. The datasheet details the device architecture, peripheral set, memory organization, and packaging options.
Key sections cover operating ranges, CPU core features, DMA, communication modules, motor‑control peripherals, ADCs, flash and SRAM capacities, power‑management options, and pin‑out diagrams, enabling designers to select the appropriate variant for their embedded system.
| Maximum MIPS | 40 MIPS @ 3.0‑3.6 V |
|---|---|
| CPU data path width | 16‑bit |
| Instruction width | 24‑bit |
| Program memory address space | Up to 4 M instruction words |
| Data memory address space | Up to 64 KB |
| Flash program memory size | Up to 256 KB |
| Data SRAM size | Up to 30 KB (incl. 2 KB DMA RAM) |
| Digital I/O pins | Up to 85 programmable pins |
| On‑chip voltage regulator | 2.5 V regulator |
| Operating voltage | 3.3 V |
| Package options | 64‑, 80‑, 100‑pin TQFP |
Each dsPIC33F device provides up to 256 KB of flash program memory.
The controller offers up to 85 programmable digital I/O pins.