This document provides design suggestions to enable a smooth transition from the QSLAC device to the newer QLSLAC™ device. The goal is to develop a design that is fully software compatible for both SLAC™ devices with a minimal number of hardware modifications. Considerations are given for linecard designs using Zarlink’s solid state Subscriber Line Interface Circuits (SLIC) device as well as transformer SLIC device designs.
The guide explains how to transition line‑card designs from the 5 V QSLAC device to the lower‑voltage QLSLAC device while keeping software compatibility and minimizing hardware changes. It covers power‑supply requirements, subscriber line interface circuit options, and microprocessor interface timing.
Key topics include device similarities and differences, power‑supply considerations, solid‑state and transformer SLIC designs, filter‑coefficient computation, and interface specifications such as MPI timing and frame‑synchronization requirements.
| QSLAC power supply voltage | 5.0 V ±5% |
|---|---|
| QLSLAC power supply voltage | 3.3 V ±5% |
| Current per device | ≥ 55 mA |
| Digital input voltage tolerance | 5.0 V tolerant |
| Frame‑synchronization pulse | 8 kHz |
The QSLAC device requires a 5.0 V power supply within a ±5 % tolerance.
Each device should be able to source at least 55 mA of current.
Both devices need an 8 kHz frame‑synchronization pulse applied to the FS pin.