The HC138/HC238/HCT138/HCT238 are high speed silicon gate CMOS decoders well suited to memory address decoding or data routing applications. The HC138 and HC238 feature low power consumption typically associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL logic. The HC/HCT138 series has eight normally high outputs, of which, if the device is enabled, these inputs determine which one will go low or which of the normally low outputs of the HC/HCT238 series will go high. Two active low and one active high enables (E1, E2 and E3) are used to simplify cascading.
The CD54/74HC138, CD54/74HCT138, CD54/74HC238, and CD54/74HCT238 are high‑speed CMOS 3‑to‑8 line decoders with three enable inputs, low power consumption and TTL compatible outputs. They are suited for memory decoding and data routing applications and feature balanced propagation delay and transition times.
The devices are offered in CERDIP, PDIP, SOIC and SSOP packages. Electrical specifications include a supply voltage range of 2 V to 6 V for HC types and 4.5 V to 5.5 V for HCT types, a typical propagation delay of 13 ns, and an operating temperature range of –55 °C to 125 °C. Absolute maximum ratings and detailed pin‑out diagrams are provided.
| Operating Temperature Range | -55 °C to 125 °C |
|---|---|
| Typical Propagation Delay | 13 ns |
| Enable Inputs | Three (E1, E2, E3) |
| Package Options | CERDIP, PDIP, SOIC, SSOP |
The decoder provides three enable inputs (E1, E2, E3) to simplify cascading.
Typical propagation delay is 13 ns at a 5 V supply.
They are offered in CERDIP, PDIP, SOIC and SSOP packages.