NVIDIA CUDA Programming Guide is an official NVIDIA CUDA programming guide that introduces CUDA programming model, hardware implementation and API.
This guide introduces the CUDA parallel computing architecture and its programming model, covering threads, blocks, grids, and memory hierarchy. It also describes the CUDA hardware implementation and device compatibility.
Subsequent chapters detail the CUDA runtime and driver APIs, including function qualifiers, memory management, texture handling, and interoperability with OpenGL and Direct3D. The document concludes with performance guidance, a matrix multiplication example, and technical specifications of CUDA-capable devices. This manual is written in Chinese.
| Maximum threads per block | 512 |
|---|---|
| Maximum block dimensions (x, y, z) | 512 × 512 × 64 |
| Warp size | 32 threads |
| Registers per multiprocessor | 8192 |
| Shared memory per multiprocessor | 16 KB |
A CUDA block can contain up to 512 threads.
A warp consists of 32 threads.
The maximum block dimensions are 512 threads in x, 512 in y, and 64 in z.
Each multiprocessor provides 16 KB of shared memory.