Industrial

74LCX374 is a low voltage CMOS octal D-type non-inverting flip-flop fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for both inputs and outputs. These 8 bit D-Type flip-flops are controlled by a clock input (CK) and an output enable input (OE). On the positive transition of the clock, the Q outputs will be set to the logic state that were setup at the D inputs. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. The Output control does not affect the internal operation of flip flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. It has same speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption and higher compatibility.

This document provides information on the 74LCX125 low-voltage CMOS quad bus buffer. The product features 5V tolerant inputs and outputs, high-speed response, low power consumption, and is suitable for automotive, industrial, computer, and consumer applications.

74LCX74 is a low voltage CMOS dual D-type flip flop with preset and clear non inverting fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for inputs. A signal on the D INPUT is transferred to the Q OUTPUT during the positive going transition of the clock pulse. CLR and PR are independent of the clock and accomplished by a low setting on the appropriate input. It has same speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

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This document describes the features and characteristics of the 74LCX86 low voltage CMOS quad Exclusive OR gate with 5V tolerant inputs. It features high speed operation, power down protection on inputs and outputs, symmetrical output impedance, balanced propagation delays, and compatibility with 74 series 86. It is designed for low power and high speed 3.3V applications and can be used in a 5V signal environment.

The 74LCX32 is a low voltage CMOS quad 2-input OR gate with features such as 5V tolerant inputs, high speed, and low power consumption. It is ideal for low power and high speed 3.3V applications and can be interfaced to a 5V signal environment for inputs. The product is equipped with protection circuits against static discharge, providing 2KV ESD immunity and transient excess voltage protection. It is fabricated using sub-micron silicon gate and double-layer metal wiring C2MOS technology.

The 74LCX14 is a low voltage CMOS HEX SCHMITT inverter with 5V tolerant inputs.

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This document describes a low voltage CMOS quad 2-input AND gate with features such as 5V tolerant inputs, high speed, power down protection, etc. It is suitable for low power and high speed 3.3V applications and can be interfaced to a 5V signal environment. The product has good ESD performance and transient excess voltage protection.

The 74LCX04 is a low voltage CMOS HEX inverter fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.

The 74LCX02 is a low voltage CMOS quad 2-input NOR gate fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for inputs. It has same speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

The document describes the features and characteristics of the 74LCX245 low voltage CMOS octal bus transceiver. It has 5V tolerant inputs and outputs, and is suitable for low power and high speed 3.3V applications. This product is intended for two-way asynchronous communication between data buses, with the direction of data transmission determined by the DIR input. The enable input G can be used to disable the device, effectively isolating the buses. All inputs and outputs are equipped with protection circuits against static discharge, providing 2KV ESD immunity and transient excess voltage protection. All floating bus terminals during the High Z state must be held HIGH or LOW.

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