Micrel Manuals

The SY10/100E446 are integrated 4-bit parallel-to-serial data converters. These devices are designed to operate for NRZ data rates of up to a minimum of 1.3Gb/s. The chips generate a divide-by-4 and a divide-by-8 clock for both 4-bit conversion and a two-chip 8-bit conversion function. The conversion sequence was chosen to convert the parallel data into a serial stream from bit D0 to D3. A serial input is provided to cascade two E446 devices for 8-bit conversion applications. The SYNC input will asynchronously reset the internal clock circuitry. This pin allows the user to reset the internal clock conversion unit and, thus, select the start of the conversion process. The MODE input is used to select the conversion mode of the device.

The SY10/100E445 are integrated 4-bit serial-to-parallel data converters. The devices are designed to operate for NRZ data rates of up to 2.5Gb/s. The chip generates a divide-by-4 and a divide-by-8 clock for both 4-bit conversion and a two-chip 8-bit conversion function. The conversion sequence was chosen to convert the first serial bit to Q0, the second to Q1, etc. Two selectable serial inputs provide a loopback capability for testing purposes when the device is used in conjunction with the E446 parallel-to-serial converter. The start bit for conversion can be moved using the SYNC input. When asynchronously applied for a period of time, a single pulse will lock the conversion to the selected input.

The SY10/100E431 are 3-bit flip-flops with differential clock, data input and data output. The asynchronous Set and Reset controls are edge- triggered rather than level controlled. This allows the user to rapidly set or reset the flip-flop and then continue clocking at the next clock edge without the necessity of de-asserting the set/reset signal (as would be the case with a level controlled set/reset). The E431 is also designed with larger internal swings, an approach intended to minimize the time spent crossing the threshold region and thus reduces the metastability susceptibility window.

The SY100E417 is a quint LVPECL-to-PECL translator. It can also be used as a quint PECL-to-LVPECL translator. The device receives standard PECL signals and translates them to differential LVPECL output signals (or vice versa). The SY100E417 can also be used as a differential line receiver for PECL-to-PECL or LVPECL-to-LVPECL signals.

The SY10/100E416 are 5-bit differential line receiving devices. The 2.0GHz of bandwidth provided by the high frequency outputs make the devices ideal for buffering of very high speed oscillators. A VBB pin is available to AC couple an input signal to the devices. The design incorporates two stages of gain internal to the devices, making them an excellent choice for use in high bandwidth amplifier applications.

The SY10/100E404 are 4-bit differential AND/NAND devices, ideal for pulse shaping applications where duty cycle skew is critical. The differential inputs and outputs allow for their use as fully differential 2-input OR/NOR functions. The output RISE/FALL times of these devices are significantly faster than most other standard ECLinPS devices, resulting in an increased bandwidth. The differential inputs have clamp structures which will force the Q output of a gate in an open input condition to go to a LOW state. Thus, inputs of unused gates can be left open and will not affect the operation of the rest of the device.

The SY10/100E337 is a 3-bit registered bus transceiver with scan designed for use in new, high-performance ECL systems. It features a maximum clock to bus (data transmit) of 1500ps, a maximum clock to Q (data receive) of 1000ps, an extended 100E VEE range of –4.2V to –5.5V, 25Ω cutoff bus outputs, 50Ω receiver outputs, etc.

The SY10/100E336 is a bus transceiver designed for use in new, high-performance ECL systems. It features a 25Ω cutoff bus output, an extended -4.2V to -5.5V VEE range, a 50Ω receiver output, transmit and receive registers, a maximum clock to bus of 1500ps, a maximum clock to Q of 1000ps, internal edge slow-down capacitors on bus outputs, additional package ground pins, full compatibility with industry standard 10KH, 100K ECL levels, internal 75KΩ input pulldown resistors, and full compatibility with Motorola MC10E/100E336. It is available in a 28-pin PLCC package.

SY100E310L is a 3.3V, precision 2:8 ECL/PECL fanout buffer optimized for precision low-skew clock distribution. The SY100E310L features fully differential clock paths to minimize both device and system skew resulting in skew performance of < 50ps. In addition, the device includes a 2:1 multiplexer input for redundant switchover applications. The SY100E310L is optimized for low voltage +3.3V LVPECL or –3.3V LVECL applications.

The document describes a 3-bit 4:1 multiplexer-latch called SY10/100E256, which has features such as extended VEE range, separate select controls, differential outputs, and full compatibility with industry standard 10KH, 100K ECL levels.

This document is the functional description of SY10/100E241 8-bit scannable register, including timing diagram and pin definition, and details its data input, output, register operation and other characteristics

The SY100E222L is a low-skew, low-jitter device capable of receiving a high-speed LVECL/LVPECL input in either a single-ended or differential configuration. For single-ended configurations, a VBB output reference is supplied by the SY100E222L. A 2:1 input multiplexer selects from two differential input pairs by means of the CLK_SEL input select. The internal programmable divider for each of the four banks generates a ÷1 or ÷2 frequency of the selected input. The ÷1/÷2 divider outputs can be asynchronously synchronized with the master reset (MR) input so that the outputs will start out in a known state. The 15 total outputs are partitioned into four independently selected output banks in a 2/3/4/6 fano.

SY10/100E212 are scannable registered ECL drivers typically used as fan-out memory address drivers for ECL cache driving. They feature an extended VEE range, a maximum CLK to Output delay of 1025ps, dual differential outputs, and are fully compatible with industry standard 10KH, 100K ECL levels and Motorola MC10E/100E212.

The SY10/100E196 are programmable delay chips (PDCs) designed primarily for very accurate differential ECL input edge placement applications.

The SY10E195/100E195 are programmable delay chips (PDCs) designed primarily for clock de-skewing and timing adjustment. They provide variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in the logic diagram. The first two delay elements feature gates that have been modified to have delays 1.25 and 1.5 times the basic gate delay of approximately 80ps. These two elements provide the E195 with a digitally-selectable resolution of approximately 20ps. The required device delay is selected by the seven address inputs D[0:6], which are latched on-chip by a high signal on the latch enable (LEN) control. If the LEN signal is either LOW or left floating, then the latch is transparent. Because the delay programmability of the E195 is achieved by purely differential ECL gate delays, the device will operate at frequencies of >1GHz, while maintaining high push-pull outputs, suitable for a wide variety of circuit applications.