Micrel Manuals

The SY100S834/L is a low skew (÷1, ÷2, ÷4) or (÷2, ÷4, ÷8) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be AC-coupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the SY100S834/L under single-ended input conditions. As a result, this pin can only source/sink up to 0.5mA of current. The Function Select (FSEL) input is used to determine what clock generation chip function is. When FSEL input is LOW, SY100S834/L functions as a divide by 2, by 4 and by 8 clock generation chip. However, if FSEL input is HIGH, it functions as a divide by 1, by 2 and by 4 clock generation chip. This latter feature will increase the clock frequency by two folds. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal clock of maximum frequency of 100MHz.

SY10/100EL16VA-VF are differential receivers. The devices are equivalent to SY10/100EL16 or SY10/ 100EL16V with enhanced capabilities. The QHG, /QHG outputs have a DC gain several times larger than the DC gain of the Q output. The SY10/100EL16VA have an identical pinout to the SY10/100EL16 or SY10/100EL16V. It provides a VBB output for either single-ended application or as a DC bias for AC coupling to the device. The SY10/100EL16VB are very similar to the SY10/ 100EL16VA. The /Q output is provided for feedback purposes. The SY10/100EL16VC provides an /EN input which is synchronized with the data input (D) signal in a way that provides glitchless gating of the QHG and /QHG outputs. When the /EN signal is LOW, the input is passed to the outputs and the data output equals the data input. When the data input is HIGH and the /EN goes HIGH, it will force the QHG LOW and the /QHG HIGH on the next negative transition of the data input. If the data input is LOW when the /EN goes HIGH, the next data transition to a HIGH is ignored and QHG remains LOW and /QHG remains HIGH. The next positive transition of the data input is not passed on to the data outputs under these conditions. The QHG and /QHG outputs remain in their dis- abled state as long as the /EN input is held HIGH. The /EN input has no influence on the /Q output and the data input is passed on (inverted) to this output whether /EN is HIGH or LOW. This configuration is ideal for crystal oscillator applica- tions, where the crystal oscillator provides the clock.

The SY100EL15L is a low skew 1:4 clock distribution IC designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to be used the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the EL15 under single-ended input conditions. As a result, this pin can only source/sink up to 0.5mA of current. The EL15 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high-speed system clock. When LOW (or left open and pulled LOW by the input pull-down resistor) the SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. When both differential inputs are left open, CLK input will pull down to VEE and CLK input will bias around VCC/2.

The SY10/100EL15 is a low skew 1:4 clock distribution chip designed specifically for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to be used the VBB output should be connected to the CLK input and bypassed to VCC via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the EL15 under single- ended input conditions, as a result this pin can only source/sink up to 0.5mA of current. The EL15 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pull-down resistor) the SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/ disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input.

The SY10/100EL12 are low-impedance drive buffers. With two pairs of OR/NOR outputs, the devices are ideally suited for high drive applications such as memory addressing. These devices are functionally equivalent to the E112 devices, with higher performance capabilities. With propagation delays significantly faster than the E112, the EL12 is ideally suited for those applications which require the ultimate in AC performance.

SY10EL11V SY100EL11V are 1:2 differential fanout buffers with 5V/3.3V power supply options, 265ps propagation delay, 5ps skew between outputs, high bandwidth output transitions, internal 75KΩ input pull-down resistors, replaces SY10/100EL11, improved output waveform characteristics, available in 8-pin SOIC package.

The SY100EL1003 is a high-speed current source used to drive a semiconductor laser diode in optical transmission applications. It operates at up to 1.25Gbps and has a peak drive current of 75mA. The device has differential inputs for data, separate modulation control and output enable pins for laser safety. It operates with a single power supply and is available in a 16-pin SOIC package.

SY10/100EL05 are 2-input differential AND/NAND gates. These devices are functionally equivalent to the E404 devices, with higher performance capabilities. With propagation delays and output transition times significantly faster than the E404, the EL05 is ideally suited for those applications which require the ultimate in AC performance. Because a negative 2-input NAND is equivalent to a 2-input OR function with inverted inputs, the differential inputs and outputs of the device allows the EL05 to also be used as a 2-input differential OR/NOR gate. The differential inputs employ clamp circuitry so that, under open conditions (pulled down to VEE), the input to the AND gate will be HIGH. In this way, if one set of inputs is open, the gate will remain active to the other input.

The SY10/100EL04 are 2-input AND/NAND gates with 240ps propagation delay, high bandwidth output transitions, internal 75KΩ input pull-down resistors and available in 8-pin SOIC package.

The SY10EL01/100EL01 are 4-input OR/NOR gates with 230ps propagation delay, high bandwidth output transitions and 75KΩ input pull-down resistors, ideal for applications requiring the ultimate in AC performance.

The SY10/100E457 are 3-bit differential 2:1 multiplexers. The fully differential data path makes the devices ideal for multiplexing low skew clock or other skew sensitive signals. Multiple VBB pins are provided to ease AC coupling input signals. The higher frequency outputs provide the device with a >1.0GHz bandwidth to meet the needs of the most demanding system clock. Both separate selects and a common select are provided to make the device well suited for both data path and random logic applications.

The SY10/100E452 is a 5-bit differential register with differential data inputs and outputs and a clock. It features an inverted master reset input and asynchronous master reset, making it suitable for high-frequency applications.

The SY10/100E451 is a 6-bit register with single-ended outputs and differential data and clock inputs, designed for use in new, high-performance ECL systems. The registers are triggered by the rising edge of the CLK input. A logic HIGH on the Master Reset (MR) input resets all outputs to a logic LOW. The VBB output is provided for use as a reference voltage for single-ended reception of ECL signals to that device only. Features include a minimum toggle frequency of 1100MHz, extended -4.2V to -5.5V VEE range, internal 75KΩ input pulldown resistors, etc.