IDT Manuals

The MK3807-01 is a low skew 3.3V, 1 to 10 fanout buffer. The large fanout from a single input line reduces loading on the input clock. The TTL level outputs reduce noise levels on the part. Typical applications are clock and signal distribution.

The IDT74LVC374A is an industrial temperature range 3.3V CMOS octal edge-triggered D-type flip-flop. It is built using 0.5-micron CMOS technology and features ESD protection of over 2000V. The device supports hot insertion and has rail-to-rail output swing for increased noise margin. It is suitable for 5V and 3.3V mixed voltage systems.

IDT74GTLP16612 is an 18-bit universal bus transceiver that provides signal level translation from TTL to GTLP for applications requiring a high-speed interface between cards operating at TTL logic levels and back-planes operating at GTLP logic levels.

IDT54/74FCT88915TT is a low-jitter PLL clock driver launched by IDT. The operating frequency range is 10MHz-133MHz. There are 5 non-inverting outputs, 1 inverted output, 1 2x output and 1 1/2x output at the output port. All output ports are TTL-compatible. The output voltage range is 3V-5V and the output current is 64-15mA.

IDT54/74FCT240/244T/AT/CT/DT - 2240/2244T/AT/CT, IDT54/74FCT540/541/2541T/AT/CT FAST CMOS OCTAL BUFFER/LINE DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES

This document describes the features and characteristics of IDT's products, including high-performance 64-bit microprocessor, single/double precision floating-point unit, high-speed caches, and flexible bus interface.

This document describes the features and characteristics of the FIFO dual-port memory from Integrated Device Technology, Inc., including the 64 x 4 or 64 x 5 organization, low power consumption, high-speed data communications applications, etc.

This document describes the features and characteristics of IDT72261LA and IDT72271LA CMOS SuperSync FIFOs, including memory organizations, read/write cycle time, data latency time, low power mode, reset functions, data status flags, etc.

The IDT71V3577/79 are high-speed SRAMs organized as 128K x 36/256K x 18. The IDT71V3577/79 SRAMs contain write, data, address and control registers. There are no registers in the data output path (flow-through architecture). Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the IDT71V3577/79 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter tracks the address during burst mode to ensure that data is provided to the system during the burst.

IDT70V27S/L is a dual-port memory produced by IDT company. It has high-speed access, low power consumption, separate upper and lower byte control, dual chip enables, bus width expansion, busy flag and interrupt flag, port arbitration logic, semaphore logic, fully asynchronous operation and other features.

This document is a functional block diagram of DSC-5632/3 published by Integrated Device Technology, Inc. in November 2003. It includes features such as busy and interrupt flags, on-chip port arbitration logic, full on-chip hardware support of semaphore signaling between ports, fully asynchronous operation from either port, separate byte controls, dual-port memory cells, high performance and high reliability.

IDT6116SA/LA is a high-performance static RAM manufactured by IDT company using CMOS technology. It has fast access and low power consumption. The product has military and commercial temperature ranges and meets the MIL-STD-833, Class B standard.

IDT72V3686/96/106 3.3 VOLT CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING, is an integrated circuit product produced by IDT company. It has the following features: 1. Storage capacity: IDT72V3686 - 16,384 x 36 x 2 IDT72V3696 - 32,768 x 36 x 2 IDT72V36106 - 65,536 x 36 x 2 2. Clock frequency: up to 100MHz (6.5ns access time) 3. Independent FIFO buffers can be used between a bidirectional 36-bit port and two unidirectional 18-bit ports (Port C receives and Port B transmits) 4. Supports 18-bit (word) and 9-bit (byte) bus sizing, 18 bits (word) on Ports B and C 5. Select IDT Standard Timing (using EFA, EFB, FFA, and FFC flag functions) or First Word Fall Through Timing (using ORA, ORB, IRA, and IRC flag functions) 6. Programmable Almost-Empty and Almost-Full flags, each with five default offsets (8, 16, 64, 256, and 1024) 7. Serial or parallel programming of partial flags 8. Big- or Little-Endian format for word and byte bus sizes 9. Loopback mode on Port A 10. Retransmit Capability 11. Master Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings 12. Mailbox bypass register