IDT Manuals

128K x 8 high performance CMOS static RAM

The document describes a product released in November 2003. The product is a 256/128K x 36 memory array with dual-port memory cells, asynchronous operation, and byte controls.

IDT70P35/34L is a high-performance 1.8V 8/4K x 18 dual-port static RAM with low power consumption and high speed. It has independent upper-byte and lower-byte control for multiplexed bus compatibility.

This PDF file is an introduction document about IDT49FCT805BT/CT and IDT49FCT806BT/CT products. It mainly introduces the features and characteristics of the products, including 0.5 micron CMOS process, low jitter, low power consumption, TTL compatible inputs and outputs, high drive, two independent output circuits, anti-static electricity and so on

The FCT3805/A is a 3.3 volt, non-inverting clock driver built using advanced dual metal CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and its own output enable control. The device has a "heartbeat" monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. The FCT3805/A offers low capacitance inputs with hysteresis. The FCT3805/A is designed for high speed clock distribution where signal quality and skew are critical. The FCT 3805 also allows single point-to-point transmission line driving in applications such as address distribution, where one signal must be distributed to multiple receivers with low skew and high signal quality.

Low-voltage 12-bit 1:2 mux / demux bus switch with internal pull down resistors

This document describes the features of IDT7132SA/LA and IDT7142SA/LA high-speed 2K x 8 dual-port static RAM. The product features high-speed access, low-power operation, expandable data bus width, port arbitration logic, BUSY output flag, battery backup operation, TTL compatibility, etc.

This data sheet provides detailed information about the FCT646T/648T/652T and FCT2646T/2652T, including features, characteristics, and applications.

The IDT54/74FCT377T/AT/CT/DT are octal D flip-flops built using an advanced dual metal CMOS technology. They have eight edge-triggered, D-type flip-flops with individual D inputs and O outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s O output. The CE input must be stable only one set-up time prior to the LOW-to-HIGH transition for predictable operation. IDT54/74FCT377T/AT/CT/DT is a fast CMOS octal D flip-flop with clock enable, suitable for military and commercial temperature ranges.

FCT374T/FCT2374T, FCT534T and FCT574T/FCT2574T are 8-bit registers built using an advanced dual metal CMOS technology. These registers consist of eight D-type flip-flops with a buffered common clock and buffered 3-state output control. When the output enable (OE) input is LOW, the eight outputs are enabled. When the OE input is HIGH, the outputs are in the high-impedance state. Input data meeting the set-up and hold time requirements of the D inputs is transferred to the Q outputs on the LOW-to-HIGH transition of the clock input. The FCT2374T and FCT2574T have balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot and controlled output fall times-reducing the need for external series terminating resistors. FCT2xxxT parts are plug-in replacements for FCTxxxT parts.

This document is a detailed introduction of IDT54/74FCT821A/B/C IDT54/74FCT823A/B/C IDT54/74FCT824A/B/C IDT54/74FCT825A/B/C HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS

IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT are high-performance CMOS bus interface registers from Integrated Device Technology, Inc., suitable for military and commercial temperature ranges.

The FCT257T is a high-speed quad 2-input multiplexer built using an advanced dual metal CMOS technology. This product has low input and output leakage, CMOS power levels, True TTL input and output compatibility, high drive outputs, meet or exceed JEDEC standard 18 specifications, military product compliant to MIL-STD-883, Class B and DESC listed (dual marked)

This document is the product manual of IDT71V2556/58 3.3V high-speed synchronous SRAM devices. It introduces the features and characteristics of the devices, including 128K x 36, 256K x 18 memory configurations, 200 MHz high performance system clock speed, ZBTTM feature, single R/W control pin, 4-word burst capability, individual byte write control, three chip enables, 3.3V power supply, 2.5V I/O supply, JEDEC standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA).