ATMEL Manuals

The document describes an embedded system using the ARM7TDMI processor, which features high performance, high-density instruction set, and low power consumption. It includes 256KB internal high-speed flash and 32KB internal high-speed SRAM.

The document describes a single-chip solution that incorporates the ARM920T™ ARM® Thumb® processor, offering high performance and low power consumption. It also includes internal memories, an external bus interface, and various system peripherals that provide support for enhanced performance.

This document introduces the features and characteristics of the LPC2101 MCU

This document introduces the features and characteristics of STM32F103C8T6, which uses the ARM7TDMI® ARM® Thumb® processor core with a high-performance 32-bit RISC architecture and a high-density 16-bit instruction set, and is the leader in MIPS/Watt.

This article introduces the architecture of Atmel PLD products and the timing calculation methods. It also mentions the tools and software packages that design engineers can use. Atmel PLDs have deterministic and path-independent delays, which greatly simplify timing calculation.

This document is an application note for ATV2500, which introduces how ATV2500 is used to incorporate multiple control or logic functions into a single programmable logic device

Atmel announced the availability of the ATF2500C, the highest density CPLD available in a 40-pin or 44-pin package. The ATF2500C is reprogrammable using Atmel's proven EE-based technology and is pin-compatible with the ATV2500B/BQ/BQL/BL which were OTP devices. The ATV2500B/BQ will be replaced by ATF2500C for commercial and industrial grade devices.

This document describes how to use the features of the ATV2500 and ATV2500B in the ABEL (and Atmel- ABEL) and CUPL (and Atmel-CUPL) high level description languages. The ATV2500 and ATV2500B are the most powerful programmable logic devices available in a 40/44-pin package. They combine high density and global routing, making them easy to use and understand. Both devices have 24 macrocells, each with three sum terms, two regis- ters, and 17 product terms. Each register has individual clock and AR product terms. Each I/O pin has a programmable polarity control and an individual output enable product term. Independent feed- back paths from each register allow all of the registers to be buried without wasting the I/O pins. A universal bus routes all input and feedback signals to all product terms on all macrocells. The ATV2500B has the additional features of D- or T-type configurable registers, three dif- ferent clock options, and buried combinatorial nodes.

This document introduces the low-power features of Atmel PLDs, including the various density classes of Atmel PLDs and Atmel PLD's Input Transition Detection (ITD) technology. Atmel PLD's Input Transition Detection technology can significantly reduce power consumption.

This document introduces how to use programmable logic devices as system controllers based on I/O buses

This document describes how to use the features of the ATV750 and ATV750B in the ABEL and CUPL high level description languages. The ATV750 and ATV750B are easy upgrades from a 22V10, offering twice the logic density and more flexibility in the same footprint. Both devices have 20 registers and individual clock and AR product terms for each register. Each I/O pin has a programmable polarity control and an individual output enable product term. Independent feedback paths from each register allow all of the registers to be buried without wasting the I/O pins. For the ATV750B, the registers can also be configured as D- or T-type and the clock can be selected as either a synchronous clock pin or a clock product term.

This application note describes the differences between the ATV750B/BL PLD and the ATF750C/CL PLD, including features, packages, temperature grades, etc.

This white paper introduces a method for improving the I/O connectivity and logic reusability of Complex Programmable Logic Devices (CPLDs). This method, called Logic Doubling, works by splitting the logic circuit into two logic blocks and using different logic circuits in each logic block. This allows CPLDs to support more I/O ports and improve the reusability of logic circuits.

This document is a user guide for Atmel ATF15xx Family ISP Devices, providing information on the features and usage of the devices.

This product is a high-density, high-performance, electrically erasable complex programmable logic device, with features of 64 macrocells, 5 product terms per macrocell, expandable to 40 per macrocell, 44, 68, 84, 100 pins, maximum pin-to-pin delay of 7.5 ns, registered operation speed up to 125 MHz, and enhanced routing resources