Analog Devices Manuals

The 12-Output Clock Generator with Integrated 1.6 GHz VCO AD9517-4 Rev. D is a clock generator from Analog Devices. The product has low phase noise, phase-locked loop (PLL), 1 pair of 1.6 GHz LVPECL outputs, 2 pairs of 800 MHz LVDS clock outputs etc.

AD9517-3 is an output clock generator with an integrated 2.0 GHz VCO. It features low phase noise, a phase-locked loop (PLL), automatic revertive and manual reference switchover/holdover modes, multiple reference input interfaces, programmable delays, digital or analog lock detect, etc.

The AD9517-1 is a 12-output clock generator with an integrated 2.5 GHz VCO. The clock generator features a low phase noise, phase-locked loop (PLL). The AD9517-1 supports 1 differential or 2 single-ended reference inputs and has reference monitoring capability. In addition, the clock generator supports automatic revertive and manual reference switchover/holdover modes and accepts LVPECL, LVDS or CMOS references to 250 MHz. The AD9517-1 has a programmable delay path to the PFD and supports digital or analog lock detect. The clock generator has 2 pairs of 1.6 GHz LVPECL outputs, each output pair shares a 1:32 divider with coarse phase delay. Additive output jitter is 225 fs rms, channel-to-channel skew paired outputs are <10 ps. The AD9517-1 also has 2 pairs of 800 MHz LVDS clock outputs, each output pair shares two cascaded 1:32 dividers with coarse phase delay. Additive output jitter is 275 fs rms, fine delay adjust (Δt) is supported on each LVDS clock output.

AD9517-0 is a 12-output clock generator with integrated 2.8 GHz VCO. It features low phase noise, automatic switchover modes, and programmable delays.

AD9516-4 is a 14-channel clock generator with integrated 1.6 GHz VCO.

The AD9516-3 is a 14-output clock generator with integrated 2.0 GHz VCO, providing low phase noise, phase-locked loop (PLL) functionality, and accepting LVPECL, LVDS or CMOS references up to 250 MHz.

AD9516-2 is a 14-channel clock generator with an integrated 2.2 GHz VCO.

This document describes the AD9516-1 Rev. B model, a 14-output clock generator with an integrated 2.5 GHz VCO. It features a low phase noise PLL, supports multiple reference inputs, has automatic switchover and holdover modes, and provides multiple LVPECL and LVDS clock outputs.

AD9515 is a 1.6GHz clock distribution IC with divider, delay adjustment, and two outputs.

The AD9514 is a 1.6GHz clock distribution IC that includes 3 programmable dividers, delay adjustment, and three outputs.

The document introduces AD9513 Rev. 0, an 800 MHz clock distribution integrated circuit with dividers, delay adjust, and three outputs. It is suitable for low jitter, low phase noise clock distribution and can be used in applications such as high-speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs, high-performance wireless transceivers, high-performance instrumentation, and broadband infrastructure.

The AD9510 is a 1.2 GHz clock distribution IC with a PLL core, dividers, delay adjust, and eight outputs. It features low phase noise, programmable dual-modulus prescaler, programmable charge pump, separate CP supply, two 1.6 GHz differential clock inputs, 8 programmable dividers, phase select for output-to-output coarse delay adjust, 4 independent 1.2 GHz LVPECL outputs, additive output jitter of 225 fs rms, 4 independent 800 MHz/250 MHz LVDS/CMOS clock outputs, additive output jitter of 275 fs rms, fine delay adjust on 2 LVDS/CMOS outputs, and a serial control port. The AD9510 is suitable for low jitter, low phase noise clock distribution and high-speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs, and other applications.

The ADN2855 is a burst mode clock and data recovery IC designed for GPON/BPON/GEPON optical line terminal (OLT) receiver applications. The device can operate at 155.52 Mbps, 622.08 Mbps, 1244.16 Mbps or 1250.00 Mbps serial data input. It features 12-bit acquisition time, 4-bit parallel LVDS output interface, patented dual-loop clock recovery architecture, integrated PRBS generator, byte rate reference clock, loss-of-lock indicator, supports double data rate (DDR)-compatible FPGA I2C interface to access optional features and single-supply operation (3.3 V).

ADN2819 is a high performance multirate clock and data recovery IC with integrated limiting amp, supporting up to 2.7Gb/s bandwidth.