Analog Devices Manuals

The AD9523-1 is a low jitter clock generator with 14 LVPECL/LVDS/HSTL/29 LVCMOS outputs

AD9523 Rev. B is a low jitter clock generator with 14 LVPECL/LVDS/HSTL and 29 LVCMOS outputs. It provides accurate output frequency and start-up frequency accuracy, zero delay operation, and precise input-to-output edge timing. It also features adjustable delay, output-to-output skew, automatic synchronization, and output dividers with jitter-free adjustable delay. The device has a low absolute output jitter and a wide integration range. It is controlled through a serial control port and has a dual PLL architecture.

12 LVDS/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO AD9522-4

AD9522-3 is a 12-channel LVDS/24-channel CMOS output clock generator produced by ADI. It has an integrated 2GHz VCO, supports a frequency range of 1.72-2.25GHz, supports CMOS, LVPECL or LVDS reference signals, and supports 16.62-33.3MHz crystal inputs. It supports optional reference clock doubling, automatic and manual reference switching, automatic recovery and digital or analog lock detection.

AD9515 is a low jitter, low phase noise clock distribution IC that features programmable dividers, coarse delay adjustment and 1.6 GHz LVPECL, 800 MHz/250 MHz LVDS/CMOS clock outputs. It can provide low jitter and low phase noise clock signals to high performance ADC, DAC, DDS, DDC, DUC and MxFE applications.

AD9520-5 is an AD company's clock generator product. It supports external 3.3V/5V VCO/VCXO to 2.4GHz, supports 1 differential or 2 single-ended reference inputs, supports CMOS, LVDS or LVPECL references to 250MHz, supports 16.67MHz to 33.3MHz crystal reference input, supports optional reference clock doubler, supports reference monitoring function, supports automatic and manual reference switching/holdover mode, supports selectable reverse/non-reverse switching, supports glitch-free reference switching, supports automatic recovery from holdover mode, supports digital or analog lock detection, supports optional zero delay operation, supports 12 1.6GHz LVPECL outputs, each output can be divided into 4 groups, each group of 3 outputs has a 1-to-32 divider with phase delay, output jitter is as low as 225fs rms, the channel-to-channel skew of grouped outputs is less than 16ps, each LVPECL output can be programmed as CMOS or LVPECL output.

AD9520-4 is a 12 LVPECL/24 CMOS output clock generator with integrated 1.6 GHz VCO, features low phase noise, phase-locked loop (PLL), 1 differential or 2 single-ended reference inputs, 16.67 MHz to 33.3 MHz crystal for reference input, optional reference clock doubler, reference monitoring capability, auto and manual reference switchover/holdover modes, selectable revertive/nonrevertive switching, glitch-free switchover, automatic recover from holdover, digital or analog lock detect, optional zero delay operation.

This document describes a 12 LVPECL/24 CMOS output clock generator with an integrated 2.5 GHz VCO. It supports external 3.3V/5V VCO/VCXO up to 2.4 GHz. The clock generator features a low phase noise phase-locked loop (PLL), accepts CMOS, LVDS, or LVPECL reference signals up to 250 MHz, supports automatic and manual reference switchover/holdover modes, and has 12 1.6 GHz LVPECL outputs with low additive output jitter.

The AD8184 is a high speed 4-to-1 multiplexer with a -3 dB signal bandwidth of 700 MHz and a slew rate of 750 V/µs. It offers 95 dB of crosstalk and 115 dB isolation, making it useful in many high speed applications. With a differential gain and differential phase error of 0.01% and 0.01°, and a flatness of 0.1 dB up to 75 MHz, the AD8184 is ideal for professional video multiplexing. It has a switching time of 10 ns, making it an excellent choice for pixel switching (picture-in-picture), while consuming less than 4.5 mA on ±5 V supply voltage. The AD8184 has a high speed disable feature that allows the output to be put into a high impedance state, enabling multiple outputs to be connected together for cascading stages without loading the output bus. It operates on ±5 V voltage supplies and is available in 14-lead PDIP and SOIC packages.

ADM8832 is a charge pump regulator for color TFT panels. It features multiple output voltages, power efficiency optimization, low quiescent current, fast transient response, etc.

AD9518-4 is a 6-output clock generator with integrated 1.6 GHz VCO. It features low phase noise, phase-locked loop (PLL), external VCO/VCXO up to 2.4 GHz, multiple reference inputs, programmable delays, digital or analog lock detect, etc.

AD9518-3 Rev. C is a 6-output clock generator with integrated 2.0 GHz VCO. It features low phase noise, phase-locked loop (PLL), various reference input options, programmable delays, digital or analog lock detect, etc.

AD9518-2 is a 6-channel clock generator from Analog Devices, featuring an integrated 2.2GHz VCO for low phase noise and low jitter clock output.

This product is a low phase noise, phase-locked loop (PLL) 6-output clock generator with integrated 2.5 GHz VCO. It has 1 differential or 2 single-ended reference inputs, and can accept LVPECL, LVDS or CMOS reference signals, up to 250 MHz. Digital or analog lock detect can be selected. It has 3 pairs of 1.6 GHz LVPECL outputs. Each output pair shares a 1:32 divider with coarse phase delay. Additive output jitter is 225 fs rms. Channel-to-channel skew paired outputs are less than 10 ps. All outputs are automatically synchronized on power-up. Manual output synchronization is available. This product is suitable for low jitter, low phase noise clock distributors, digital baseband and wireless communication systems.

This document describes the AD9518-0 Rev. C, a 6-output clock generator with an integrated 2.8 GHz VCO. The clock generator features a low phase noise phase-locked loop (PLL) with a tunable range from 2.55 GHz to 2.95 GHz. It also offers an optional external VCO/VCXO up to 2.4 GHz and supports 1 differential or 2 single-ended reference inputs. It accepts LVPECL, LVDS, or CMOS references up to 250 MHz and provides programmable delays and digital or analog lock detect. The device includes 3 pairs of 1.6 GHz LVPECL outputs, each pair sharing a 1-to-32 divider with coarse phase delay. It supports channel-to-channel synchronization and automatic synchronization on power-up. The clock generator is suitable for applications requiring low jitter and low phase noise clock distribution.