Microchip dsPIC33F Reference Manual

About this manual

This document provides a complete description of the dsPIC33F microcontroller family, covering interrupt architecture, vector tables, and core register definitions. It includes tables of interrupt vectors, alternate vector tables, and the layout of CPU registers used for interrupt control.

The manual also explains CPU core register fields such as IPL, SR, CORCON and how they affect interrupt priority and service routines. It lists address locations for each interrupt source and describes special features like the Fail‑Safe Clock Monitor and Power‑On Reset. This manual is written in Chinese.

What's inside

• Interrupt Vector Table (IVT)
• Alternate Interrupt Vector Table (AIVT)
• CPU Core Registers
• Interrupt Priority Levels (IPL)
• Interrupt Service Routine (ISR)
• Interrupt Request (IRQ)
• Fail‑Safe Clock Monitor (FSCM)
• Power‑On Reset (POR)

Specifications

Frequently asked questions

What is the Interrupt Vector Table (IVT)?

The IVT is a table that holds the address of each interrupt service routine for the dsPIC33F.

What does the Fail‑Safe Clock Monitor (FSCM) do?

FSCM monitors the clock and can trigger a reset if the clock fails.