Infineon M9900 A21 Security Target Lite

Security Target Lite for Infineon's M9900 A21 smart‑card security controller, detailing architecture, features and security requirements.


Infineon M9900 A21 Security Target Lite - cover page
Brand
Infineon
Document type
Other
Language
English
Pages
57
File format
PDF
File size
641 KB
Published
01 October, 2026
Updated
01 October, 2026
MD5 checksum
39BE64C494523AA46A2F674800F3E40D

About this manual

The Security Target Lite describes the Infineon M9900 A21 smart‑card security controller, a 32‑bit RISC CPU based on the ARMv7‑M architecture fabricated in 90 nm CMOS technology. It outlines the hardware components, firmware, peripherals and cryptographic co‑processors that form the target of evaluation (TOE).

The document defines the security problem, objectives, functional and assurance requirements, and provides a summary specification of the TOE, including its memory model, random number generator, and protection mechanisms against fault and side‑channel attacks.

What's inside

  • Security Target Introduction
  • Target of Evaluation Description
  • Conformance Claims
  • Security Problem Definition
  • Security Objectives
  • Extended Component Definition
  • Security Requirements
  • TOE Summary Specification
  • References
  • Glossary

Specifications

CPU architecture32‑bit RISC CPU based on ARMv7‑M
Maximum addressable memory4 GB linear address space
Random number generatorTrue Random Number Generator (TRNG) meeting AIS31 PTG2
Manufacturing technology90 nm CMOS (L90)

Frequently asked questions

What CPU architecture does the M9900 A21 use?

It uses a dedicated 32‑bit RISC CPU based on the ARMv7‑M architecture.

How much addressable memory does the M9900 A21 provide?

The controller provides up to a 4 GB linear addressable memory space.

What manufacturing process is used for the M9900 A21 chip?

The chip is fabricated in a 90 nm CMOS (L90) process.

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