This guide provides DDR3 layout and routing recommendations for i.MX 6Quad, 6Dual, 6DualLite, and 6Solo processors.
The document translates the official Freescale Hardware Development Guide and focuses on DDR3 layout and routing for i.MX 6 series application processors. It explains the importance of impedance matching, signal length matching, and placement of DDR3 devices relative to the CPU.
Key sections cover routing rules, topology options (T‑type and Fly‑by), detailed routing constraints, example board layouts, high‑speed signal recommendations, ground‑plane design, and power‑rail routing for DDR3 and VREF networks. This manual is written in Chinese.
| Single‑ended impedance | 50 Ω |
|---|---|
| Differential impedance | 100 Ω |
| Maximum DDR chips in T‑type topology | 4 chips |
| Clock length tolerance | ±5 mil |
| VREF network spacing | ≥25 mil |
The recommended impedance is 50 Ω for single‑ended traces and 100 Ω for differential pairs.
Data lines may be swapped within a byte, but swapping across bytes is not allowed.
A T‑type topology should use no more than four DDR3 chips.
VREF traces should be spaced at least 25 mil from other networks.