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The Sun Microsystems STP1010 is a highly integrated 32-bit RISC microprocessor implementing the SPARC Architecture version 8. Designed for low-cost single processor applications, it features a pipelined Integer Unit, a Floating Point Unit, and separate Instruction and Data Caches. The processor operates at a nominal internal frequency of 50 MHz, delivering a throughput of 26 SPECint92 and 21 SPECfp92.
| Operating Frequency | 50 MHz |
|---|---|
| SPECint92 Throughput | 26 |
| SPECfp92 Throughput | 21 |
| Instruction Cache Size | 4 Kbyte |
| Data Cache Size | 2 Kbyte |
| Register File | 120-word |
| Floating Point Performance | 12 MMlops peak |
| Max System Memory | 128 MBytes |
| DRAM Bus Width | 64 bits |
| SBus Data Width | 32-bit |
The processor operates at a nominal internal frequency of 50 MHz.
The STP1010 provides a complete DRAM controller which supports up to 128 MBytes of system memory.
The TAP controller implements a state diagram with 16 states as detailed in the IEEE 1149.1 protocol.