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This document is a datasheet for the Sun Microsystems STP1030A, a high-performance UltraSPARC-I microprocessor. It implements the SPARC V9 64-bit RISC architecture and supports the Visual Instruction Set (VIS) for multimedia processing, including video compression and decompression. The processor is designed to sustain up to four instructions per cycle using a superscalar design with multiple execution units.
| Architecture | SPARC V9 64-Bit RISC |
|---|---|
| Processor-Cache Bandwidth | 2.6 Gigabyte/sec |
| Processor-Memory Bandwidth | 1.3 Gigabyte/sec |
| Processor-Memory Bandwidth (High) | 1.6 Gigabyte/sec |
| Design | 4-way Superscalar |
| Integer Execution Units | 4 |
| Floating-Point Execution Units | 3 |
| Graphics Execution Units | 2 |
| Data Cache Size | 16 Kilobyte |
| Instruction Cache Size | 16 Kilobyte |
| Process Technology | 0.4um 4-Layer Metal CMOS |
| Operating Voltage | 3.3V |
| Package | 521 Pin Plastic Ball Grid Array |
The STP1030A is a high-performance, highly-integrated superscalar processor implementing the SPARC V9 64-bit RISC architecture.
The STP1030A is capable of sustaining the execution of up to four instructions per cycle even in the presence of conditional branches and cache misses.
The processor operates at 3.3V.