Sun Microsystems STP1012 microSPARC-II Data Sheet

查询STP1012PGA-110供应商


Sun Microsystems STP1012 microSPARC-II Data Sheet - cover page
Brand
Sun Microsystems
Category
Processors
Document type
Datasheet
Language
English
Pages
21
File format
PDF
File size
751 KB
Published
07 August, 2012
Updated
30 September, 2023
MD5 checksum
5D86FE72E1B504DB02C9CCBE8E261695

About this manual

This document is a datasheet for the Sun Microsystems STP1012, a high-performance SPARC v8 32-bit microprocessor. The chip features an integrated Integer Unit (IU), Floating Point Unit (FPU), and Memory Management Unit (MMU). It operates at frequencies up to 110 MHz and includes on-chip caches for instructions and data.

What's inside

  • Description
  • Features
  • Technical Overview
  • SIGNAL DESCRIPTIONS
  • Integer Unit
  • Floating Point Unit
  • Memory Management Unit
  • Instruction Cache
  • Data Cache
  • Memory Interface

Specifications

Operating Frequencyup to 110 MHz
ArchitectureSPARC Architecture v8
Instruction Cache Size16 Kbyte
Data Cache Size8 Kbyte
Package Type321-pin Ceramic PGA package

Frequently asked questions

What is the estimated SPECint92 performance?

The estimated performance is 78 SPECint92.

What is the peak floating-point performance?

The optimized Integrated Floating-Point Unit delivers 21.7 MFlops peak performance.

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