Query STP1021APGA-75 suppliers
The STP1021A is a new member of the SuperSPARC-II family designed using a state-of-the-art BICMOS process. It features a highly integrated processor subsystem on a single chip, including integer and floating-point execution units, separate instruction and data memory management units (MMU), and large level-1 caches totaling 36 KBytes.
The microprocessor supports VBus mode for connection with external cache controllers like the STP1091, as well as MBus for processor-independent connections. Key features include a high-performance IEEE754 floating-point unit, hardware integer multiply and divide, and Built-In Self Test (BIST) logic.
The processor operates at a frequency of 85MHz.
The processor includes a total of 36 KBytes of cache memory.
The MBus supports a peak transfer rate of 320 MBytes/s.