STP1020PGA-50 is an integrated circuit chip produced by STP.
The STP1020 is a highly integrated, high-performance superscalar 32-bit RISC microprocessor designed using a state-of-the-art BiCMOS process. It is fully SPARC version 8 compliant and upward compatible with earlier SPARC version 7 implementations. The processor integrates integer and floating-point execution units, a memory management unit, and large on-chip instruction and data caches on a single chip.
| Architecture | 32-Bit RISC Microprocessor |
|---|---|
| Compliance | SPARC version 8 |
| Operating Frequency | 50 MHz |
| Instruction Cache Size | 20 KByte |
| Data Cache Size | 16 KByte |
| Total Cache Memory | 36 KBytes |
| Register Windows | 8 windows |
| Bus Interface | MBus or VBus |
The STP1020 supports VBus and MBus protocols. VBus is used with an external cache controller, while MBus allows direct connection to the bus.
The mode is selected by statically connecting the CCMODE pin to Ground for VBus or pulling it high for MBus.
Yes, it is completely upward compatible with earlier SPARC version 7 implementations.