STMicroelectronics AN2352 PLL Jitter Effects on C-CAN Modules Application Note

About this manual

This document analyzes the impact of Phase Locked Loop (PLL) jitter on the C-CAN modules found in the ST10F27x, ST10R27x, ST10F25x, and ST10F296 microcontroller families. It explains how transient phase shifts introduced by PLL circuits can affect network performance and reliability.

What's inside

• Configuration of the CAN bit timing
• Bit time and bitrate
• Propagation time segment
• Phase buffer segments and synchronization
• System clock tolerance range
• Phase locked loop (PLL)
• PLL jitter
• ST10F27x PLL jitter effect in CAN protocol
• System clock tolerance range reduction
• Conclusion

Specifications

Frequently asked questions

Which ST devices are covered by this application note?

The information is valid for the ST10F27x, ST10R27x, ST10F25x and ST10F296 devices.

What is the supported range for CAN bit rates?

CAN supports bit rates in the range of less than 1 Kbit/s up to 1000 Kbit/s.