ST AN2354 Application note

This application note gives advice on using the ASC peripherals present in the ST10 and in particular, the asynchronous operations will be considered. A brief guide in the configuration of the peripheral and how to connect it to an RS232 interface or RS485 network is followed by an analysis of the sources of timing problems and how to minimize them to allow correct and error-free communications.


ST AN2354 Application note - cover page
Brand
STMicroelectronics
Category
microcontrollers
Document type
Application Note
Language
English
Pages
21
File format
PDF
File size
187 KB
Published
06 August, 2012
Updated
30 September, 2023
Model
ST10
MD5 checksum
5D1003C10568C12851425D63DDC0B1D0

About this manual

This document offers advice on utilizing the Asynchronous/Synchronous Serial (ASC) peripherals found in ST10 microcontrollers, with a specific focus on asynchronous operations. It includes a guide on configuring the peripheral and connecting it to RS232 or RS485 networks. The text also analyzes potential sources of timing problems and provides methods to minimize them for error-free communication.

The note details the functionality of the ASC interfaces, including register descriptions for control, transmit, and receive buffers. It explains asynchronous data frames, hardware error detection, baud rate generation, and interrupt control. Additionally, it covers electrical characteristics and connection examples for both RS232 and RS485 interfaces.

What's inside

  • ST10 ASC peripherals
  • Asynchronous operation
  • RS232 interface connection
  • RS485 network connection
  • UART communication timing
  • Baud rate generation
  • Hardware error detection
  • Interrupt control

Specifications

Data transfer modes8-bit or 9-bit data transfer
Baud rate generator13-bit
Error detectionParity, framing, and overrun

Frequently asked questions

What are the main differences between ASC0 and ASC1 interfaces?

The main differences are limited to the programming model and interrupt management, while general functionality and performance are equivalent.

How is the receiver enabled in asynchronous mode?

Data reception is enabled by setting the Receiver Enable bit (SxREN) in the control register.

What happens if a wrong parity bit is received?

The parity error flag (SxPE) is set along with the error interrupt request flag.

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