This application note provides instructions on how to interface two ADV202s when used in HDTV, 1080i mode. It covers topics such as interface connection, data input rate limitations, and configurations for multichip applications.
This document provides instructions on interfacing two ADV202 chips when used in HDTV 1080i mode. It details the configuration requirements, including data input rates, interface types, compression modes, and synchronization issues for multichip applications. The text specifies that SMPTE274M 1080i video at 60 fields/sec requires a total data rate of 1.485 Gbps, necessitating at least two ADV202s to manage the data input rates for 10-bit data.
The guide covers decode configurations (master/slave and slave/slave) and encode configurations, where the ADV202 is always a slave. It outlines the necessary limitations for HDTV applications, such as a maximum data input rate of 65 MSPS per ADV202 in irreversible mode and the use of the VDATA bus. The document also includes detailed programming steps for initializing and configuring the chips for multichip sync mode.
| Maximum data input rate (irreversible mode) | 65 MSPS |
|---|---|
| Maximum data input rate (reversible mode) | 32 MSPS |
| Input data rate for 1080i 10-bit data | 124 Mbytes/sec |
| VCLK frequency for 1080i application | 74.25 MHz |
| Minimum CODE FIFO size for 32-bit data | 256 32-bit words |
At least two ADV202s are required to manage the data input rates for 1080i.
The VDATA bus is recommended for uncompressed video data input or output.
The ADV202 is always a slave in encode mode.