The MPC7455 and MPC7445 are implementations of the PowerPC microprocessor family, primarily focusing on the MPC7455. This document describes the electrical and physical characteristics of the MPC7455, targeted at networking and computing systems applications.
The document describes the MPC7455, a high-performance superscalar RISC microprocessor implementing the full 32-bit PowerPC architecture. It features an on-chip L2 cache, support for external L3 SRAM caches, and includes eleven independent execution units such as integer, floating-point, and vector processing units.
The MPC7455 is a third-generation implementation of the fourth generation (G4) PowerPC RISC microprocessor family.
The on-chip Level 2 cache consists of a unified instruction and data memory with a size of 256-Kbyte.
The Level 3 cache interface supports a total of 1 or 2 Mbytes of external SRAM for L3 cache data.