This document introduces the features and characteristics of the PowerPC 601 RISC microprocessor.
This document serves as a technical summary for the PowerPC 601 RISC microprocessor, detailing its features, architecture, and implementation specifics. It highlights the processor's status as the first implementation of the PowerPC family, featuring a superscalar design capable of issuing three instructions per clock cycle.
| Data Bus Width | 64-bit |
|---|---|
| Address Bus Width | 32-bit |
| Process Technology | 3.6-V CMOS |
| Instruction Throughput | Three instructions per clock |
It is the first microprocessor from the PowerPC architecture family.
It is available from IBM as PPC601 and from Motorola as MPC601.