PML2552-35A is a 35A model of the PML2552 series of three-terminal regulators. It has a working voltage range of 27.5V to 60V and an output voltage range of 3.3V to 60V. It has a low voltage drop and high reliability.
The Philips Semiconductors PML2552 is a high-density CMOS programmable macro logic (PML) device designed for general-purpose logic integration. It provides instant gate array capabilities, allowing designers to replace large amounts of TTL, SSI, and MSI logic. The device is fabricated with a high-performance EPROM process and features a folded NAND array architecture that enables multiple levels of logic on a single chip.
| Power dissipation (TTL) | 630mW |
|---|---|
| Power dissipation (CMOS) | 525mW |
| Power dissipation (Power-down mode) | 5mW |
| Delay per internal NAND gate | 15ns (typ) |
| Flip-flop toggle rate | 50MHz |
| Number of flip-flops | 52 |
| Number of possible foldback NAND gates | 112 |
| Number of possible inputs | 53 |
| Number of possible outputs | 24 |
The delay per internal NAND gate is 15ns typical, and the flip-flop toggle rate is 50MHz.
The scan test feature allows access to internal flip-flop nodes using dedicated pins SCI (Scan In) and SCM (Scan Mode) to shift test patterns.