This document describes an enhancement-mode (normally-off) transistor that utilizes a vertical DMOS structure and Supertex's well-proven silicon-gate manufacturing process. These transistors have the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. They are ideally suited for a wide range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired.
The document describes the Supertex VP0300, a P-Channel Enhancement-Mode Vertical DMOS FET. These devices utilize advanced DMOS technology to combine the power handling capabilities of bipolar transistors with the high input impedance and positive temperature coefficient inherent in MOS devices. They are noted for being free from secondary breakdown and thermal runaway.
| Drain-to-Source Voltage (BVdss) | -30V |
|---|---|
| Gate Threshold Voltage (Vgs(th)) | -1.0 to -4.5 V |
| ON-State Drain Current (IDon) | -1.5 to -1.7 A |
| Static Drain-to-Source ON-State Resistance | 2.5 Ohms |
| Turn-ON Time (ton) | 30 ns |
| Operating Temperature Range | -55°C to +150°C |
The document lists TO-92 as a package option.
No, the document explicitly marks this product as OBSOLETE.