This document describes a high-performance system with speeds up to 100 MHz, array multipliers over 50 MHz, and flexible 10 ns SRAM. It also provides FreeRAM™, a flexible single/dual port synchronous/asynchronous 10 ns SRAM with 2,048 to 18,432 bits of distributed SRAM independent of logic cells. Additionally, the system features 128 to 384 PCI compliant I/Os, 8 global clocks, and pin-compatible package options. The system supports Cache Logic® dynamic full/partial re-configurability in-system, enabling unlimited re-programmability and fast design changes.
The document describes the Atmel AT40K/AT40KLV family of fully PCI-compliant, SRAM-based Field Programmable Gate Arrays (FPGAs). These devices range in size from 5,000 to 50,000 usable gates and feature a patented distributed 10 ns SRAM capability known as FreeRAM. The architecture supports dynamic full or partial re-configurability without data loss, allowing the FPGA to act as an adaptive coprocessor.
The AT40KLV devices require a supply voltage of 3.3V.
The FPGA supports system speeds up to 100 MHz.
The AT40K40 model provides 40,000 to 50,000 usable gates.