ST M36L0R7050T0 M36L0R7050B0 handbook

M36L0R7050T0/B0 is a 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory and 32 Mbit (2M x16) PSRAM, 1.8V Supply Multi-Chip Package, supports Synchronous Burst Read mode, 54MHz, Asynchronous Page Read mode, Random Access: 85ns, 10µs typical Word program time using Buffer Program, Multiple Bank Memory Array: 8 Mbit Banks, Parameter Blocks (Top or Bottom location), All blocks locked at power-up, Any combination of blocks can be locked with zero latency, WPF for Block Lock-Down, Absolute Write Protection with VPPF = VSS, 100,000 PROGRAM/ERASE CYCLES per BLOCK.


Brand
STMicroelectronics
File format
PDF
Published
07 June, 2012
Updated
01 October, 2023
MD5 checksum
B2FEF2B6995498E9EB5700170F77E22E
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