This document is the datasheet of the TMS320C80 digital signal processor from 1997, which describes the features and characteristics of the processor. The processor is a single-chip parallel multiple instruction/multiple data (MIMD) DSP capable of executing over two billion RISC-equivalent operations per second. It includes a master processor (MP), four parallel processors (PP), a transfer controller (TC), and a video controller (VC) among other components. It features a 32-bit RISC processor, IEEE-754 floating-point capability, instruction cache, data cache, and more. It also supports big-endian or little-endian operation, has 50K bytes of on-chip RAM, a 4G-byte address space, a 16.6-ns cycle time, and operates at 3.3V.
The TMS320C80 is a single-chip Multiple Instruction/Multiple Data (MIMD) digital signal processor capable of performing over two billion operations per second. It integrates a 32-bit Reduced Instruction Set Computing (RISC) master processor with a 120-MFLOP IEEE floating-point unit, four parallel processing DSPs, and a transfer controller.
The transfer controller supports a transfer rate of up to 480M-byte/s.
The device is capable of performing over two billion operations per second.
The processor operates with a 16.6-ns cycle time.