This file is a detailed introduction to the 6507BS chip produced by Atmel. The chip adopts the AVR Enhanced RISC Architecture architecture and has the characteristics of high performance and low power consumption. The chip has 320K Bytes of ROM Program Memory, 288K Bytes of EEPROM, 8K Bytes of RAM, and two I/O ports, ISO7816 controller, serial peripheral interface, programmable internal oscillator, two 16-bit timers, random number generator, two-level 8-way interrupt controller, 32-bit cryptographic accelerator, hardware DES and triple DES.
The document describes the AT90SC320288RCT as a low-power, high-performance 8/16-bit microcontroller based on the secureAVR enhanced RISC architecture. It is designed for smart card applications and includes advanced security features such as protection against SPA/DPA attacks and hardware-based cryptographic acceleration.
| Architecture | secureAVR Enhanced RISC Architecture |
|---|---|
| Operating Voltage Range | 1.62V to 5.5V |
| Program Memory Size | 320K Bytes |
| EEPROM Size | 288K Bytes |
| RAM Size | 8K Bytes |
| Crypto Library ROM | 32K Bytes |
| Data Retention | 10 Years |
| I/O Ports | Two I/O Ports |
It provides a highly flexible and cost-effective solution to many smart card applications.
The 32-bit Cryptographic Accelerator supports RSA, DSA, ECC, Diffie-Hellman, Hardware DES, and Triple DES.
No, it is a summary document; a complete document will be available under NDA.
Supported tools include the Voyager Emulation Platform, IAR Embedded Workbench V3.20c Debugger, and AVR Studio Version 4.07 or Above.