This document mainly introduces the characteristics and functions of dsPIC30F, including product application scenarios, characteristics, packaging, etc.
The document is a preliminary datasheet for the dsPIC30F Enhanced Flash 16-bit Digital Signal Controllers. It outlines the high-performance Modified RISC CPU features, such as the Harvard architecture, instruction set, and memory addressing capabilities.
Key peripheral features described include multiple timers, capture/compare/PWM functions, SPI, I2C, UART, CAN bus modules, and analog-to-digital converters (A/D) with support for audio codec protocols. The document also details special microcontroller features like code protection, power management modes, and self-reprogramming capabilities.
| Architecture | Modified Harvard architecture |
|---|---|
| Instruction Set Size | 84 base instructions |
| Program Memory Addressing | Linear program memory addressing up to 4M instruction words |
| Data RAM Capacity | Up to 8 Kbytes of on-chip data RAM |
| EEPROM Capacity | Up to 4 Kbytes of non-volatile data EEPROM |
| Operating Speed | Up to 30 MIPs operation |
| Clock Input Range | DC to 40 MHz external clock input |
| I/O Current Sink/Source | 25 mA/25 mA |
| A/D Converter Resolution | 12-bit Analog-to-Digital Converter (A/D) |
| Operating Voltage Range | Wide operating voltage range (2.5V to 5.5V) |
This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source.
For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual.
There are up to 41 interrupt sources with 8 user selectable priority levels.