This application note discusses the effects of clock phase noise and jitter on sampled systems and recommends considering system performance and cost when selecting clock circuits.
The note discusses the growing need for accurate clock specifications as higher‑resolution data converters become available. It explains why traditional jitter specifications are insufficient and why both wide‑band and close‑in phase‑noise characteristics must be considered when designing or selecting a clock source.
It then presents methods for estimating jitter impact on SNR, shows how phase‑modulated clock signals appear in the output spectrum, and offers practical equations and examples to predict spurious levels and overall converter performance.
| Clock jitter requirement for 70 MHz IF at 75 dB SNR | 400 femtoseconds |
|---|---|
| Encode source frequency used in example | 78 MSPS |
| Phase‑modulated sideband level in example | –66 dBc |
A clock jitter of 400 femtoseconds is required.