Analog Devices ADSP-BF536/ADSP-BF537 Datasheet

The document describes the features and characteristics of Analog Devices' TigerSHARC and Blackfin Embedded Processor ADSP-BF536/ADSP-BF537.


Analog Devices ADSP-BF536/ADSP-BF537 Datasheet - cover page
Brand
Analog Devices
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
64
File format
PDF
File size
3.5 MB
Published
04 June, 2012
Updated
29 September, 2023
MD5 checksum
76D1AA34894F7C5EC948BA285A125C8F

About this manual

The ADSP-BF536 and ADSP-BF537 are members of Analog Devices' Blackfin family, combining a high‑performance DSP core with a RISC‑like instruction set. They offer up to 600 MHz core frequency, dual 16‑bit MACs, dual 40‑bit ALUs, and extensive on‑chip memory for embedded applications.

The devices integrate a rich set of peripherals—including 10/100 Ethernet MAC, CAN 2.0B, two UARTs, SPI, TWI, dual SPORTs, nine 32‑bit timers, GPIO, RTC, and watchdog—plus flexible boot options and dynamic power management. Package options include 182‑ball MBGA and 208‑ball Sparse MBGA, supporting up to 516 MB of external memory.

What's inside

  • General Description
  • Processor Core
  • Memory Architecture
  • Peripheral Overview
  • Booting Modes
  • Event Handling
  • DMA Controllers
  • Pin Descriptions
  • Specifications

Specifications

Core frequencyUp to 600 MHz
MAC unitsTwo 16‑Bit MACs
ALU unitsTwo 40‑Bit ALUs
Core voltage range0.8 V to 1.2 V
I/O voltage tolerance2.5 V and 3.3 V‑tolerant I/O, specific 5 V‑tolerant pins
Package options182‑Ball MBGA and 208‑Ball Sparse MBGA
On‑chip memoryUp to 132 KB total (16 KB instruction SRAM/cache, 48 KB instruction SRAM, 32 KB data SRAM/cache, 4 KB scratchpad)
External memory supportUp to 516 MB external memory

Frequently asked questions

What is the maximum operating frequency of the ADSP-BF536/ADSP-BF537?

The processors can run at up to 600 MHz.

How much on‑chip SRAM is available for instructions?

The device provides 16 KB of instruction SRAM/cache and 48 KB of instruction SRAM.

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