Analog Devices EE-68 JTAG Emulator Technical Reference

About this manual

The EE-68 Engineer‑to‑Engineer Note describes how to design a JTAG emulator interface for Analog Devices DSPs. It covers the current HPPCI, HPUSB and USB JTAG emulators, their 14‑pin header, signal definitions, and the optional local boundary‑scan controller.

The document also details mechanical clearances, pod dimensions, PCB layout recommendations, power‑up sequencing, and electrical specifications such as voltage‑sense capability and supported JTAG I/O voltage levels.

What's inside

• JTAG Emulator Target Header
• JTAG Emulator Pod Mechanical Requirements
• Local Boundary Scan Controller
• Single DSP Target Connections
• Multiple DSP Target Connections
• JTAG Emulator Interface PCB Layout
• JTAG Emulator Power Sequence
• JTAG Emulator Pod Electrical Requirements
• Document History

Specifications

Frequently asked questions

Which JTAG emulators are covered by the EE-68 reference?

The current line includes the HPPCI, HPUSB and USB emulators.

What clearance is required around the JTAG emulator header?

A minimum clearance of 0.30" around the length and 0.10" around the width of the header is required.

How should the JTAG emulator be powered relative to the target board?

The JTAG emulator should be powered on and connected to the host PC before attaching it to the target header.