ATF1516AS/L is a high density, high performance electrically erasable complex programmable logic device with 256 macrocells, 5 product terms per macrocell, expandable up to 40 per macrocell, 160, 192, 208 pins, 10 ns maximum pin-to-pin delay, registered operation up to 100 MHz, enhanced routing resources
The ATF1516AS/L is a high‑performance, high‑density Complex Programmable Logic Device (CPLD) with 256 macrocells and up to 160 bidirectional I/O pins. It offers flexible macrocell configurations, including D/T/Latch flip‑flops, programmable output slew rates, and optional pin‑keeper circuits.
Key features include advanced power‑management options such as automatic standby, individual macrocell reduced‑power bits, and a power‑down mode that reduces supply current to below 3 mA. The device is programmed via a 4‑pin JTAG ISP interface compliant with IEEE Std. 1149.1 and supports boundary‑scan testing, security fuse protection, and a 16‑bit user signature.
| Number of macrocells | 256 |
|---|---|
| Maximum pin‑to‑pin delay | 10 ns |
| Registered operation speed | Up to 100 MHz |
| ESD protection | 2000 V |
| Latch‑up immunity | 200 mA |
| User signature size | 16 bits (2 bytes) |
| Package options | 160‑lead PQFP, 192‑lead PGA, 208‑lead RQFP |
The device contains 256 macrocells.
The maximum pin‑to‑pin delay is 10 ns.
It is programmed via a 4‑pin JTAG ISP interface compliant with IEEE Std. 1149.1.