This document describes the M48Z129Y* and M48Z129V models of 5.0V or 3.3V 1Mbit (128 Kb x 8) ZEROPOWER® SRAM, which feature integrated ultra-low power SRAM, power-fail control circuit, and battery. It has conventional SRAM operation, unlimited write cycles, 10 years of data retention, microprocessor power-on reset, battery low pin for end-of-life warning, automatic power-fail chip deselect and write protection, and pin and function compatibility with JEDEC standard 128K x 8 SRAM.
The M48Z129Y* and M48Z129V are ultra‑low‑power, non‑volatile SRAMs that integrate a lithium battery, aCMOS memory array and power‑fail control circuitry in a 32‑pin PMDIP package. They provide 1 Mbit (131 072 × 8) storage, unlimited write cycles, and up to ten years of data retention without power.
The document lists electrical characteristics, timing parameters, package dimensions, and ordering information, along with operating modes such as READ, WRITE, and Data Retention. It also includes maximum ratings, AC test conditions, and revision history for reference.
| Supply Voltage | 5.0 V or 3.3 V |
|---|---|
| Capacity | 1 Mbit (131 072 × 8 bits) |
| Data Retention (no power) | 10 years |
| Write Protect Voltage (M48Z129Y) | Voc = 4.5 V to 5.5 V |
| Write Protect Voltage (M48Z129V) | Voc = 3.0 V to 3.6 V |
| Operating Temperature Range | 0 °C to 70 °C |
| Package Type | 32‑pin PMDIP plastic module |
It can retain data for up to ten years when power is absent.
The M48Z129Y operates with a write‑protect voltage of 4.5 V to 5.5 V.
It is supplied in a 32‑pin plastic DIP (PMDIP) module.
The SRAM supports unlimited write cycles.