M48T59 is an integrated ultra low power SRAM, real time clock, power-fail control circuit and battery product launched by ST company. It has frequency test output, automatic power-fail chip deselect and write protection.
The M48T59, M48T59Y and M48T59V* are ultra‑low‑power 64 Kbit (8 Kbit × 8) SRAMs that include a real‑time clock, power‑fail control and a self‑contained battery and crystal in a CAPHAT™ DIP or SNAPHAT™ SOIC package. The devices are supplied for 5.0 V or 3.3 V operation and are available in both 28‑pin PCDIP (CAPHAT) and 28‑lead SOIC (SNAPHAT) form factors.
Key features include an automatic power‑fail chip‑deselect and write‑protect circuit, programmable alarm output, battery‑low flag, and a frequency‑test output for RTC calibration. The clock data is stored in dedicated memory bytes and can be accessed like any other SRAM location, while the power‑fail detection ensures data integrity during voltage drops.
| Supply Voltage | 5.0 V or 3.3 V |
|---|---|
| Memory Size | 64 Kbit (8 Kbit × 8) |
| Write‑Protect Voltage (M48T59) | 4.5 V < Vprp < 4.75 V |
| Write‑Protect Voltage (M48T59Y) | 4.2 V < Vprp < 4.5 V |
| Write‑Protect Voltage (M48T59V*) | 2.7 V < Vprp < 3.0 V |
| Package Types | 28‑pin PCDIP (CAPHAT) and 28‑lead SOIC (SNAPHAT) |
| Battery Backup | Lithium button cell integrated in CAPHAT/SNAPHAT package |
| Operating Temperature Range | 0 °C to 70 °C |
The device operates from either a 5.0 V or a 3.3 V supply.
A lithium button‑cell battery and crystal are integrated in the CAPHAT™ DIP or SNAPHAT™ SOIC package, providing backup power for the SRAM and RTC.
The series is offered in a 28‑pin PCDIP (CAPHAT) package and a 28‑lead SOIC (SNAPHAT) package.