The MAX9125/MAX9126 quad low-voltage differential signaling (LVDS) line receivers are ideal for applica- tions requiring high data rates, low power, and reduced noise.
The MAX9125 and MAX9126 are four‑channel low‑voltage differential signaling (LVDS) line receivers designed for high‑speed, low‑power applications. They translate LVDS inputs to 3.3 V CMOS outputs and operate from a single +3.3 V supply.
The MAX9126 includes integrated 115 Ω parallel termination resistors, while the MAX9125 requires an external termination resistor. Both devices support a wide common‑mode range, feature fail‑safe circuitry that forces the output high when inputs are open or shorted, and are available in 16‑pin TSSOP and SO packages.
| Maximum Data Rate | 500 Mbps (250 MHz) |
|---|---|
| Supply Voltage Range | +3.0 V to +3.6 V |
| Operating Temperature Range | -40 °C to +85 °C |
| Package Types | 16‑pin TSSOP and SO |
| Integrated Termination (MAX9126) | 115 Ω |
| Input Differential Voltage Range | 0.1 V to 1.0 V |
It forces the output high when the inputs are open, undriven and shorted, or undriven and terminated.