CAT25C128/256 is a 128K/256K-bit SPI Serial CMOS E2PROM internally organized as 16Kx8/32Kx8 bits. Catalyst’s advanced CMOS Technology substantially reduces device power requirements. CAT25C128/256 features a 64-byte page write buffer. The device operates via the SPI bus serial interface and is enabled through a Chip Select (CS). In addition to the Chip Select, the clock input (SCK), data in (SI) and data out (SO) are required to access the device. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. CAT25C128/256 is designed with software and hardware write protection to protect data from accidental erasure.
This document describes the CAT25C128/256 SPI serial CMOS EEPROM, including its features, electrical characteristics, pin assignments, and functional operation. It covers package options, absolute maximum ratings, reliability data, and detailed timing specifications for read, write, and protection functions.
The datasheet also explains the instruction set, status register bits, block protection scheme, and design considerations such as power‑up behavior and standby mode. Ordering information and temperature‑range options for commercial, industrial, and automotive grades are provided at the end.
| Operating Voltage | +1.8 V to +6.0 V |
|---|---|
| Program/Erase Cycles | 100,000 cycles |
| Data Retention | 100 years |
| Package Options | 8‑Pin DIP, 8‑Pin SOIC, 16‑Pin SOIC, 14‑Pin TSSOP, 20‑Pin TSSOP |
| Write Current | 10 mA (write) |
| Read Current | 2 mA (read) |
| Standby Current | 0 nA |
The device operates from +1.8 V to +6.0 V.
It supports up to 100,000 program/erase cycles.
The EEPROM retains data for 100 years.
The WP pin is the Write Protect pin, controlled by the WPEN bit.