National Semiconductor DS90C387/DS90CF388 Dual Pixel LVDS Display Interface (LDI) Manual

The DS90C387/DS90CF388 is a transmitter/receiver pair that supports dual pixel data transmission between the host and flat panel display up to QXGA resolutions. It offers multiple modes and features, including dual pixel data transmission, single pixel data transmission, and interoperability with FPD-Link devices.


National Semiconductor DS90C387/DS90CF388 Dual Pixel LVDS Display Interface (LDI) Manual - cover page
Brand
National Semiconductor
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
26
File format
PDF
File size
526 KB
Published
04 May, 2012
Updated
29 September, 2023
MD5 checksum
84224044FFE59CD4EC85BBF98D5A9205

About this manual

The DS90C387/DS90CF388 transmitter/receiver pair provides dual‑pixel LVDS data transmission for high‑resolution flat‑panel displays. It converts 48‑bit dual‑pixel data into eight LVDS streams and supports up to QXGA panel resolutions.

Key features include pre‑emphasis and DC‑balancing for reduced cable loading, cable deskew up to +/-1 LVDS data‑bit time, and compliance with the OpenLDI and ANSI/TIA/EIA‑644 LVDS standards. Electrical specifications such as maximum dual‑pixel rate, supply currents, and voltage ranges are detailed in the document.

What's inside

  • General Description
  • Features
  • Absolute Maximum Ratings
  • Electrical Characteristics
  • Recommended Transmitter Input Characteristics
  • Transmitter Switching Characteristics
  • Receiver Switching Characteristics
  • AC Timing Diagrams
  • Pin Diagram
  • Physical Dimensions

Specifications

Maximum dual pixel rate112 MHz
LVDS data line speed672 Mbps
Total throughput5.38 Gbps (672 Megabytes per second)
Cable deskew capability+/-1 LVDS data bit time (up to 80 MHz clock rate)
Supply voltage range (DS90C387)-0.3 V to +4 V

Frequently asked questions

What panel resolutions does the DS90C387/DS90CF388 support?

It supports SVGA through QXGA panel resolutions.

What is the maximum LVDS data line speed of the device?

The LVDS data line can operate at up to 672 Mbps.

How does the device handle cable skew?

It provides a cable deskew function of +/-1 LVDS data‑bit time, effective up to an 80 MHz clock rate.

Download PDF (526 KB)

More National Semiconductor Manuals


View all National Semiconductor manuals →