The DP83847 is a full feature single Physical Layer device with integrated PMD sublayers to support both 10BASE-T and 100BASE-TX Ethernet protocols over Category 3 (10 Mb/s) or Category 5 unshielded twisted pair cables. The DP83847 is designed for easy implementation of 10/100 Mb/s Ethernet home or office solutions. It interfaces to Twisted Pair media via an external transformer. This device interfaces directly to MAC devices through the IEEE 802.3u standard Media Independent Interface (MII) ensuring interoperability between products from different vendors. The DP83847 utilizes on chip Digital Signal Processing (DSP) technology and digital Phase Lock Loops (PLLs) for robust performance under all operating conditions, enhanced noise immunity, and lower external component count when compared to analog solutions.
The DP83847 is a single‑port Ethernet PHY supporting 10BASE‑T and 100BASE‑TX over Category 3 or 5 unshielded twisted‑pair cables. It interfaces to MAC devices via the IEEE 802.3u Media Independent Interface (MII) and includes on‑chip DSP, PLLs, and auto‑negotiation features.
The document provides pin descriptions, electrical specifications, timing diagrams, package dimensions, and recommended layout guidelines for designers integrating the device into LAN or embedded applications.
| Power consumption (typical) | < 351 mW |
|---|---|
| Technology | Low‑power 3.3 V CMOS |
| I/O voltage tolerance | 5 V tolerant I/Os |
| MAC interface voltage | 5 V/3.3 V |
| Reference clock frequency | 25 MHz |
| Package type | 56‑pin Leadless Leadframe Package (LLP) |
| Package dimensions | 56 mm × 0.5 mm × 7.8 mm (L × W × H) |
The DP83847 typically consumes less than 351 mW of power.
The reference clock input requires a 25 MHz signal.
The device is supplied in a 56‑pin leadless leadframe package.
The I/Os are 5 V tolerant and operate with a 5 V/3.3 V MAC interface.