NATIONAL SEMICONDUCTOR - LM4308 Mobile Pixel Link Two (MPL-2) 18-bit CPU Display Interface Master/Slave handbook

The LM4308 device adapts a 18-bit CPU style display interfaces to a MPL-2 SLVS differential serial link for displays. Two chip selects support a main and sub display up to and beyond 640 x 480 pixels. A mode pin configures the device as a Master (MST) or Slave (SLV). Both WRITE and READ operations are supported. CPU interface widths below 18-bits are supported by tieing unused inputs to a static level. The differential line drivers and receivers conform to the JEDEC SLVS Standard. When noise is picked up as common-mode, it is rejected by the receivers. This is further enhanced with the 50 Ohm output impedance of the drivers. The 100 Ohm termination is integrated into the receivers. Data integrity is insured with a 5-bit CRC field. CRC checking is done for both WRITE and READ operations. An Error (ERR) pin reports the occurrence of an error. A Write Only mode is also provided. The interconnect is reduced from 23 signals to only 4 active signals with the LM4308 chipset easing flex interconnect design, size constraints and cost. A low power sleep state entered when the PD* inputs are driven low.


NATIONAL SEMICONDUCTOR - LM4308 Mobile Pixel Link Two (MPL-2) 18-bit CPU Display Interface Master/Slave handbook - cover page
Brand
National Semiconductor
Category
Other Electronics
Document type
User Manual
Language
English
Pages
26
File format
PDF
File size
1.1 MB
Published
04 May, 2012
Updated
28 September, 2023
MD5 checksum
4124E7F1CE84325DF3C07B39503BE3B9

About this manual

The LM4308 adapts an 18‑bit CPU style display interface to a Mobile Pixel Link Two (MPL‑2) SLVS differential serial link. It supports master or slave operation, both write and read transactions, and reduces the interconnect to only four active signals, simplifying board layout and lowering cost.

Key features include support for up to 640 × 480 VGA formats, a 400 mVpp differential signal swing, internal 100 Ω termination, low‑power sleep mode, and a 5‑bit CRC for data integrity. Detailed pin descriptions, absolute maximum ratings, electrical characteristics, and timing diagrams are provided for designers.

What's inside

  • General Description
  • Features
  • System Benefits
  • Pin Descriptions
  • Absolute Maximum Ratings
  • Electrical Characteristics
  • Switching Characteristics
  • Recommended Input Timing Requirements
  • Functional Description
  • Serial Bus Timing

Specifications

Maximum display resolution640 × 480 VGA
Differential signal swing400 mVpp
Termination resistor100 Ω internal
Clock frequency range9.6 MHz – 30 MHz
Number of active signals4
CRC for data integrity5‑bit

Frequently asked questions

What maximum display resolution does the LM4308 support?

It supports up to 640 × 480 VGA formats.

How many signal lines are required for the LM4308 interface?

Only four active signal lines are needed.

What is the differential signal swing of the LM4308?

The device provides a 400 mVpp differential signal swing.

Does the LM4308 include an internal termination resistor?

Yes, it has an internal 100 Ω termination resistor.

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