The DP83865 is a fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-T, 100BASE-TX and 1000BASE-T Ethernet protocols. The DP83865 is an ultra low power version of the DP83861 and DP83891. It uses advanced 0.18 um, 1.8 V CMOS technology, fabricated at National Semiconductor’s South Portland, Maine facility. The DP83865 is designed for easy implementation of 10/100/1000 Mb/s Ethernet LANs. It interfaces directly to Twisted Pair media via an external transformer. This device interfaces directly to the MAC layer through the IEEE 802.3u Standard Media Independent Interface (MII), the IEEE 802.3z Gigabit Media Independent Interface (GMII), or Reduced GMII (RGMII). The DP83865 is a fourth generation Gigabit PHY with field proven architecture and performance. Its robust performance ensures drop-in replacement of existing 10/100 Mbps equipment with ten to one hundred times the performance using the existing networking infrastructure.
The DP83865 Gig PHYTER V is a fully featured Ethernet physical layer transceiver supporting 10/100/1000 Mb/s operation. It integrates PMD sublayers, offers ultra‑low power consumption, and interfaces directly to twisted‑pair media via an external transformer. The device provides MII, GMII and RGMII interfaces and includes programmable pins for flexibility.
The datasheet details the pin description, management and media‑dependent interfaces, electrical specifications, layout recommendations, and a comprehensive FAQ section that addresses common integration questions. Physical dimensions and package information are also provided for board‑level design.
| Power consumption | typically 1.1 W |
|---|---|
| Supported clock operation | 25 MHz with crystal or oscillator |
| Supply requirements | 1.8 V core/analog and 2.5 V analog/I‑O |
| Package | 128‑pin PQFP (14 mm × 20 mm) |
No, the PHY can start up without accessing any MDIO registers.
The document suggests checking configuration settings and LED status to resolve link‑only operation.
The datasheet lists the Auto‑Negotiation process but does not specify an exact duration.
Master/Slave mode is determined by the hardware configuration when Auto‑Negotiation is disabled.