Intersil X4163/X4165 16K × 8‑Bit CPU Supervisor Datasheet

X4163, X4165 16K, 2K x 8 Bit CPU Supervisor with 16K EEPROM is a low-power CPU monitor produced by Intersil. It has optional watchdog timer, low voltage detection and reset assertion.


Intersil X4163/X4165 16K × 8‑Bit CPU Supervisor Datasheet - cover page
Brand
Intersil
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
21
File format
PDF
File size
316 KB
Published
04 May, 2012
Updated
30 September, 2023
MD5 checksum
20369619314E96E46C080D1BE2F98CE8

About this manual

The X4163 and X4165 devices combine a power‑on reset circuit, selectable watchdog timer, low‑voltage detection and a 16‑Kbit (2K × 8) serial EEPROM in a single package. They provide system protection by holding the RESET/RESET pin active during power‑up, low‑voltage conditions, or watchdog timeout, and include non‑volatile control bits for configuring thresholds and protection features.

The devices are offered in 8‑lead SOIC and 8‑lead TSSOP packages, operate from 2.7 V to 5.5 V (or 4.5 V‑5.5 V for specific versions), and support a 400 kHz 2‑wire serial interface for EEPROM access. Detailed pin configurations, control‑register programming procedures, and timing diagrams are provided for system integration.

What's inside

  • Description and Features
  • Pin Configuration
  • Power‑On Reset Operation
  • Low‑Voltage Monitoring
  • Watchdog Timer
  • EEPROM Write Protection
  • Voc Threshold Programming
  • Control Register
  • Serial Interface
  • Packaging and Ordering Information

Specifications

EEPROM size16 Kbit (2 K × 8)
Standby current (watchdog on)<20 µA
Standby current (watchdog off)<1 mA
Reset signal valid to Vcc1 V
Package types8‑Lead SOIC, 8‑Lead TSSOP
Package types8‑Lead TSSOP
Temperature range (-40 °C – 85 °C)-40 °C – 85 °C
Watchdog timer period control bitsWD1 and WD0
Serial interface speed400 kHz 2‑wire

Frequently asked questions

What does the RESET/RESET pin do?

RESET/RESET is an active low/high open‑drain output that goes active on power‑on reset, low‑voltage detection, or watchdog timeout and stays active until the voltage recovers.

How is the watchdog timer period selected?

The period is set by programming the two non‑volatile bits WD1 and WD0 in the control register.

How can the low‑voltage threshold be programmed?

By setting the WEL bit, applying the desired voltage to the Voc pin and a programming voltage to the WP pin, then writing the new value to the control register.

What package options are available for the X4163/X4165?

Both devices are offered in 8‑lead SOIC and 8‑lead TSSOP packages.

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