This document provides information on a product called uPSD34xx Turbo Plus Series, which is a fast Turbo 8032 microcontroller with USB and programmable logic capabilities. It features a 40MHz advanced core with 4-clocks per instruction, delivering a peak performance of 10 MIPs. The product also includes JTAG debug and in-system programming, a 16-bit internal instruction path for fetching double-byte instructions in a single memory cycle, and a branch cache and 4 instruction prefetch queue. It supports dual flash memories with memory management, allowing the placement of either memory into the program or data address space. The product offers read-while-write operation for in-application programming and EEPROM emulation, as well as single voltage program and erase with 100K guaranteed erase cycles and 15-year retention. It also features clock, reset, and power supply management, with SRAM being battery backup capable, a flexible 8-level CPU clock divider register, normal, idle, and power down modes, a power-on and low voltage reset supervisor, and a programmable watchdog timer. Additionally, the product provides 16 macrocells for general-purpose logic applications and includes an 8-channel, 10-bit resolution A/D converter and a USB v2.0 full-speed communication interface.
The uPSD34xx Turbo Plus series combines an 8051‑based 8‑bit 8032 MCU running at up to 40 MHz with dual flash memories, SRAM, a 10‑bit ADC, USB 2.0 full‑speed, UARTs, SPI, I²C and programmable logic macrocells. It offers high performance with a 4‑cycle core, branch cache, prefetch queue and flexible clock dividers, delivering up to 10 MIPS.
The handbook provides a complete hardware description, memory organization, register set, peripheral interfaces, power‑saving modes, debugging via JTAG, and detailed notes on USB operation, I/O voltage tolerance, and revision history, helping developers design and program embedded applications.
| CPU core | Fast 8‑bit 8032 MCU, 40 MHz |
|---|---|
| Peak performance | 10 MIPS at 40 MHz (5 V) |
| SRAM | Up to 32 KB |
| ADC | 8‑channel, 10‑bit, 6 µs conversion |
| USB interface | USB 2.0 full‑speed, 10 endpoint pairs, 64‑byte FIFO each |
| UARTs | Two UARTs, up to 115 kbaud IrDA |
| I/O pins | Up to 46 I/O, 5 V tolerant (except Port 1) |
The uPSD34xx runs at up to 40 MHz.
It provides 10 endpoint pairs, each with a 64‑byte FIFO.
The flash memory is rated for 100 K guaranteed erase cycles.
No, Port 1 shares the ADC and is not 5 V tolerant.