Blackfin is a dual-core embedded processor from Analog Devices, with each core running up to 500 MHz. Each core features two 16-bit MACs, two 40-bit ALUs, and a 40-bit barrel shifter. The processor utilizes a RISC-like register and instruction model for ease of programming and compiler-friendly support. It also offers advanced debug, trace, and performance monitoring capabilities. Additionally, it provides a pipelined Vision Processor for hardware processing of signal and image algorithms used for pre- and co-processing of video frames in ADAS or other video processing applications.
The ADSP-BF606 is a dual‑core symmetric Blackfin processor that delivers up to 500 MHz per core while maintaining low static power consumption. It combines a DSP‑style signal‑processing engine with a RISC‑like instruction set, making it suitable for automotive, industrial, instrumentation, and motor‑control applications.
The handbook details the processor’s memory hierarchy (L1 SRAM, L2 SRAM, cache), extensive peripheral set (USB OTG, CAN, UART, Ethernet MAC, GPIOs), DMA and CRC engines, and event‑handling architecture. It also describes package information, pin multiplexing, and system‑level features such as the Core Event Controller and Trigger Routing Unit.
| L1 SRAM per core | 148 KB |
|---|---|
| L2 SRAM per core | Up to 256 KB |
| Maximum core speed | 500 MHz |
| Maximum SYSCLK | 250 MHz |
| Speed grade options | 400 MHz / 500 MHz |
| Package type | 349‑ball CSP_BGA |
| GPIO pins | 112 |
| USB OTG interfaces | 1 |
| Ethernet MAC (IEEE 1588) | 2 |
| L1 Instruction SRAM | 64 KB |
| L2 Data SRAM | 128 KB / 256 KB |
Each core can run up to 500 MHz.
The device includes 112 general‑purpose I/O pins.
It is supplied in a 349‑ball (19 mm × 19 mm) RoHS‑compliant BGA package.
The processor provides USB OTG, CAN, UART, and Ethernet MAC (IEEE 1588) interfaces.