This document describes the features and characteristics of the GE TOR IRQ Control/Watchdog Timer Blackfin Embedded Symmetric Multiprocessor, including dual symmetric 600 MHz high-performance Blackfin cores, 328K bytes of on-chip memory, advanced debug, trace, and performance monitoring.
The ADSP-BF561 processor is a high‑performance member of the Blackfin family, featuring dual 600 MHz symmetric cores, 328 KB of on‑chip memory and a wide range of peripherals such as DMA controllers, timers, UART with IrDA, and programmable flags. It supports low‑power operation with dynamic voltage and frequency scaling and offers multiple package options including 256‑ball CSP_BGA and 297‑ball PBGA.
The document provides a complete memory map, description of the core architecture, event handling mechanisms, and booting options. It also lists detailed specifications for peripherals, power management, and external memory interfaces, making it a comprehensive reference for designers integrating the ADSP‑BF561 into industrial, telecommunications or portable applications.
| Core frequency | 600 MHz |
|---|---|
| On‑chip memory | 328 KB |
| Package options | 256‑ball CSP_BGA (2 sizes) and 297‑ball PBGA |
| DMA controllers | Dual 12‑channel DMA controllers (supporting 24 peripheral DMAs) |
| Timers/counters | 12 general‑purpose 32‑bit timers/counters with PWM capability |
| UART | UART with IrDA support |
| Watchdog timers | Dual watchdog timers |
| PLL multiplication range | 0.5× to 64× |
The processor uses dual symmetric 600 MHz Blackfin cores.
It includes 328 KB of on‑chip memory.
The device is offered in 256‑ball CSP_BGA (two sizes) and 297‑ball PBGA packages.