DS92001 is a 3.3V B/LVDS-BLVDS buffer that accepts a BLVDS input signal and provides a BLVDS output signal. The device can accept LVPECL, CML as well as LVDS signals, and has TRI-STATE outputs, a receiver input threshold of less than ±100 mV, a propagation delay of 1.4 ns (typical), and very low jitter.
The DS92001 B/LVDS‑BLVDS Buffer converts a BLVDS input signal to a BLVDS output signal and can also translate LVDS, LVPECL, or CML inputs. It is optimized for multidrop backplanes with stub lengths up to several centimeters, providing a slow edge transition to tolerate longer stubs.
Key features include a single +3.3 V supply, input thresholds below +100 mV, fast typical propagation delay of 1.4 ns, low jitter operation up to 400 Mbps, tri‑state outputs, and availability in SOIC and leadless leadframe (LLP) packages. Electrical specifications cover supply voltage range 3.0‑3.6 V, output short‑circuit current up to 60 mA, and extensive AC performance data.
| Supply Voltage (Vcc) | 3.0 V – 3.6 V (typ 3.3 V) |
|---|---|
| Propagation Delay (typ) | 1.4 ns |
| Receiver Input Threshold | < +100 mV |
| Low Jitter Data Path | 400 Mbps |
The device operates from a single +3.3 V supply with a permissible range of 3.0 V to 3.6 V.
The typical propagation delay is 1.4 ns.
The receiver input threshold is less than +100 mV.